Verilog is a hardware description language that allows you to describe the digital system, electronic circuits, memory, or a microprocessor. Verilog can be used for time analysis, test analysis, and logic synthesis. You can design and verify digital circuits at a register-transfer level of abstraction. These description languages differ from the software programming language as they are used to model the hardware. Verilog works well if you have the hardware specifications handy. It has a simple C like structure and requires digital logic knowledge.
VHDL and Verilog are both languages for hardware description. These languages allow you to write programs for electronic chips or digital systems that do not share the computer's basic architecture. VHDL is a little older and based on Ada and Pascal and inherits both characteristics. If VHDL scripts are not strongly typed, then it is difficult to get them compiled. Since VHDL is a strongly typed language, it does not allow variables from different classes.
But on the other hand, Verilog is based on the C programming language and uses weakly typed language. Verilog is case sensitive.
VHDL and Verilog are general-purpose digital system language while the SystemVerilog specifies the Verilog's enhanced version. Each of them has their unique usage and characteristics. VHDL has Ada and pascal syntax and concept while programming, Verilog has C programming language model and concept.
VHDL is strongly typed while Verilog has simple syntax, so extra coding will be required for VHDL to convert one data type to others. VHDL has better error debugging methods and better portability between different tools.
SystemVerilog is different, which allows the developers to verify more complex designs. It is considered to be the combination of both VHDL and Verilog that uses C and C++ language.
There is some difference when it comes to coding and the understanding of the code. On the one hand, VHDL is more verbose, thus making use of more lines of code than Verilog that has C-like syntax and is much easier to code. VHDL has better code flow, while Verilog is more compact and more suitable for hardware modeling. It's up to you what type of language suits for your coding style.